In the following description, reference is made to microelectronic die, carrier substrate, microelectronic device, and microelectronic package. A microelectronic die comprises a die substrate upon which microcircuits are formed. Examples of die substrates include, among others, wafers comprising silicon (Si), gallium arsenide (GaAs), Indium Phosphate (InP) and their derivations. Various techniques are used, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic integrated circuit (IC) devices in the form of transistors, resistors, and others, on the microelectronic die. The IC devices are interconnected to define a specific electronic circuit that performs a specific function, such as the function of a microprocessor or a computer memory.
A microelectronic device is defined as a microelectronic die electrically interconnected with a carrier substrate. A carrier substrate is a structure comprising conductive pathways through which microcircuits of the microelectronic die communicate with external components. A microelectronic package is defined as a microelectronic device that is assembled into a finished package with additional components, such as electrical interconnects, a die lid, and a heat dissipation device, among others. An example of a microelectronic package includes, but is not limited to, a flip-chip ball grid array (FC-BGA) microprocessor package.
The surface of the microelectronic die that comprises the active circuitry includes one or more alternating dielectric and conductive layers. The dielectric layers are also known as passivation layers or interlayer dielectric (ILD) layers. The ILD layers electrically insulate the active circuitry from electrical shorts, but also, along with the conductive layers, define electrical communication paths terminating with land pads on the surface of the microelectronic die. The land pads provide a conductive surface upon which electrical interconnections can be made with bond pads of similar design located on the carrier substrate. A reflowable electrically conductive interconnect material is used to interconnect the land pads with the bond pads in a process commonly known as a reflow process or a controlled collapse chip connection (C4) process.
FIG. 1 is a cross sectional view of a representation of a microelectronic die 8 in the land pad region 9, comprising a die substrate 10, multiple conductive layers 14, 18, 22, ILD layers 12, 16, 20, and vias 25 that define conductive paths from a circuit on the die substrate 10 to a land pad 24 at the surface of the microelectronic die 8. The representation is not drawn to scale as the conductive and dielectric layers are exceedingly thin.
As the drive for smaller and thinner microelectronic packaging continues, materials having a low dielectric constant (k) that can be made very thin are being investigated for use as ILD material. An ILD having a lower k can be made thinner for the same performance as one that is thicker with a higher k.
Materials having a lower k tend to be structurally weak. Low k materials currently being evaluated include, among others, in order of hardness: SiO2 with a hardness of 10 GPa, SiOF with a hardness of 8.5 GPa, and carbon doped oxide (CDO) having a hardness of 2 GPa. New ultra low-k materials are approaching dielectric constants as low as k=2. One approach to providing a low-k material is to provide a material with a high pore volume. Unfortunately, as the pore volume is raised, the mechanical properties deteriorate. Many of the issues related to these mechanical properties do not necessarily show up during microelectronic die 8 manufacturing, but do arise as the microelectronic die 8 is packaged, because the packaging itself is mechanically the most challenging process.
The process used to interconnect the land pad 24 of a microelectronic die 8 and the bond pad of a carrier substrate (not shown), induces significant stress in the land pad region 9 in and around the land pad 24. The materials used for the interconnect material 30, the land pad 24, the ILD layers 12, 16, 20 and the conductive layers 12, 16, 22 each have a different coefficient of thermal expansion (CTE) and therefore, each expand and contract at different rates during thermal loading. The packaging process involves many thermal cycles, each of which can cause interlayer delamination and cracking failure due to the mismatch of CTE.
In addition to the CTE mismatch, the land pad region 9 encounters additional forces caused by the dynamics of the interconnect material 30 during the reflow process. Factors inducing these forces include, but are not limited to, the molten interconnect material 30 supporting the weight of the microelectronic die 8 during the reflow process (see FIG. 3), and the adhesion of the interconnect material 30 on the land pad 24. These forces tend to add additional stress to an already stressed laminate structure of the land pad region 9, including the ILD layer 12, 16, 22, due to the CTE mismatch, potentially causing cracking and delamination failure.
As an illustration of the potential for structural failure of the land pad region 9, a microelectronic die having the low-k material carbon doped oxide (CDO) for the ILD material was interconnected with a carrier substrate using eutectic Sn—Ag interconnect material. A commonly used reflow temperature of 230-235 C was used to interconnect copper land pads to copper bond pads with the Sn—Ag interconnect material. The stress induced at the interconnect and within the ILD material as a consequence of the reflow process caused cracking and delamination failure at the ILD and conductive layers.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for methods for interconnecting microelectronic die and carrier substrate that address the limitations and undesirable characteristics associate with the low-k ILD materials.